1. Field of the Invention
The present invention relates to the field of data storage and retrieval, and in particular, data storage and retrieval from semiconductor memories.
2. Background of the Invention
In today""s computer environment, DRAMs are one of the dominant memory technologies. DRAMs are the preferred choice for large main memories because they are inexpensive, fast and consume little power.
DRAMs are typically manufactured in discrete semiconductor packages having different input/output (I/O) data widths of, for example, four, eight, or sixteen output data bits, and are thus referred to as x4, x8, or x16 DRAMs, respectively. The number of data bits that a computer can simultaneously address and manipulate, i.e., the computer bus width, is typically much larger than that commonly available with DRAMs. For example, computers produced today may have bus widths of 32, 64, or 128 bits. To accommodate these bus widths, groups of DRAMs are packaged together to form single memory modules, for example, DIMMs (Dual In-line Memory Modules) or SIMMs (Single In-line Memory Modules).
FIG. 1 is a block diagram showing a proposed 64 bit DIMM including eight x8 DRAMs 108, 110, 112, 114, 116, 118, 120 and 122. IC chipset 102 latches data as one sixty-four bit word from/to DRAMs 108 through 122 and then, when appropriate, transmits/receives the sixty-four bit word on computer bus 124. Central Processing Unit (CPU) 125 is connected to bus 124. Computer bus 124 couples the memory system shown to other sections of the computer. Each DRAM 108-122 includes an 8 bit data out (DQ) bus 106 and a one bit clock-out 104. For clarity, the detailed structure of the DIMM address and enable lines are not shown.
The data from each DRAM 108-122 is transferred to/from IC chipset 102 synchronously. That is, when DRAM 108 outputs data to its data bus 106, it simultaneously raises its clock-out line 104. IC chipset 102 latches the received data from data bus 106 when it detects the raised clock signal.
Load capacitance and signal line length introduce propagation delays in any signal transmitted from the DRAMs 108 through 122 to IC chipset 102. Accordingly, although data may be transmitted simultaneously from DRAMs 122 and 108, data transmitted from DRAM 122 can arrive at IC chipset 102 before data from DRAM 108. In this situation, to receive data from all the DRAMs 108 through 122 in the absence of clock-out signals, IC chipset 102 must wait for the propagation delay associated with each DRAM to resolve itself before initiating latching of all 64 bits. As a result, a long waiting period is required which undesirably restricts the maximum frequency at which the DIMM 100 can operate.
A separate clock line has been proposed on each DRAM, as shown in FIG. 1, in order to overcome the above-described problem. Although the eight data bits from DRAM 108 will experience a different propagation delay than the eight data bits from DRAM 122, for example, the DRAM data is transmitted simultaneously with its own clock signal. Because the data lines and clock lines from, for example, DRAM 108, see the same capacitive load and signal line length, the propagation delays are approximately the same (i.e., the lines are matched), and the clock and data signals therefore arrive simultaneously. This allows the IC chipset 102 to latch the data received from each of DRAMs 108-122 in response to the received clock signal, thereby minimizing the delay encountered with the DIMMs discussed above.
Consumers in the computer industry desire a modular, easily upgradeable memory. To meet this demand, manufacturers have developed modular memory systems which allow additional DIMMs to be added.
FIG. 2 is a block diagram of a memory system illustrating a memory system constructed from multiple DIMMs. DIMM 200 includes eight x8 DRAMs 206 through 213 and DIMM 202 has four x16 DRAMs 214 through 217. To simplify FIG. 2, only eight-bit data bus lines 220 and 221 coupling the data outputs of DRAMs 206, 207, and 214 to data path IC 204 are shown. Although not shown, similar data buses connect DRAM groups 208, 209, and 215; 210, 211, and 216; and 212, 213, and 217. DIMM 200 has eight clock-outs connected to corresponding clock lines, one for each DRAM 206 through 213. The clock lines from DRAMs 206 and 207 are illustratively labeled as lines 224 and 225, respectively. DIMM 202 has four clock-outs, so each one is connected to two clock lines from DIMM 200. For example, the clock output 223 of DRAM 214 is coupled to clock lines 224 and 225. Likewise, the clock line 232 of DRAM 215 is connected to clock lines 226 and 227. Further, although not shown in FIG. 2, DIMMs 200 and 202 are connected to IC chipset 204 through a common address bus. Additionally, IC chipset 204 couples DIMMs 200 and 202 to CPU 229 through bus 228.
Occasionally, upgrade DIMMs purchased by the consumer are made from DRAMs of different data widths. As a result, one DIMM will have more clock lines than the other. This is shown in FIG. 2, in which DIMM 200 has eight clock lines and DIMM 202 has four clock lines. Because DRAMs 206 through 213 each have eight data lines, their respective clock-outs can be directly connected to the clock input of IC chipset 204. Each clock line from the x16 DRAM, however, must be split and connected in parallel to two x8 DRAM clock lines.
Splitting the clock lines from the x16 DRAMs 214 through 217 solves the problem of having a different number of clock lines between DIMMs 200 and 202, but introduces a new problem: splitting the clock line from DRAMs 214 through 217 introduces additional capacitive loads seen by the clock lines, but does not change the capacitive load seen by the data lines. Thus, the load seen by the DRAM clock line is no longer matched to the load of its corresponding data line, thereby introducing differences in the signal propagation time (also called signal skew). As explained above, differences in the signal propagation time between the clock and data signals decrease the speed at which the memory system can operate.
The advantages and purpose of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The advantages and purpose of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
To attain the advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a dynamic random access memory (DRAM) arranged on a single integrated circuit is provided. The DRAM has a plurality of clock outputs and a plurality of data outputs, a first portion of the plurality of clock outputs being used to synchronously transfer a first portion of the plurality of data outputs.
Further, in another embodiment of the invention, a computer memory is provided which comprises a first memory module including a first plurality of memory components, each of which having a plurality of first data outputs and at least one timing signal output. A second memory module is further provided having a second plurality of memory components, each of which having a plurality of second data outputs and at least one timing signal output, a number of the first plurality of memory components is different than a number of the second plurality of memory components. A plurality of data lines couples each of the plurality of first data outputs of each of the first plurality of memory components to a respective one of each of the plurality of second data outputs of each of the second plurality of memory components. In addition, a plurality of timing signal lines couple each of the timing signal outputs of each of the first plurality of memory components to a respective one of the timing signal outputs of the second plurality of memory components in a one-to-one corresponden
Further, in accordance with the present invention, a data processing system is provided which comprises a first memory module including a first plurality of memory components, each of which having a plurality of first data outputs and at least a first timing signal output, and a second memory module including a second plurality of memory components, each of which having a plurality of second data outputs and at least a second timing signal output, a number of said first plurality of memory components is different than a number of said second plurality of memory components. A plurality of data lines couple each of the plurality of first data outputs of each of the first plurality of memory components to a respective one of each of the plurality of second data outputs of each of the second plurality of memory components. In addition, a data routing circuit of the data processing system is coupled to each of the plurality of data lines and at least selected ones of the first and second timing signal outputs of the first and second memory modules, respectively, wherein a ratio of a number of first data outputs to a number of first timing signal outputs coupled to the data routing circuit equals a ratio of a number of second data outputs to a number of second timing signal outputs coupled to the data routing circuit.
Moreover, a method of making a computer memory is provided comprising the steps of: providing a first memory module having a first plurality of memory components, each of which having a plurality of first data outputs and at least one timing signal output; providing a second memory module having a second plurality of memory components, each of which having a plurality of second data outputs and at least one timing signal output, a number of the first plurality of memory components is different than a number of said second plurality of memory components; coupling each of the plurality of first data outputs of each of said first plurality of memory components to a respective one of each of the plurality of second data outputs of each of the second plurality of memory components; and coupling each said at least one timing signal output of each of the first plurality of memory components to a respective one of the at least one timing signal output of the second plurality of memory components, whereby the capacitive load associated with each of the first and second data outputs is equal to a capacitive load associated with each of the first and second timing signal outputs.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.